The present invention relates to power gating of an integrated circuit (IC).
The proliferation of the number of components on an IC increases power consumption. With an increase in power consumption, optimization of the power supplied to various parts in the IC becomes essential. This optimization can be achieved by electrically separating a switchable portion in the IC from a portion that requires continuous power supply. To provide power supply to these electrically separated portions, various techniques for power gating of an IC have been developed.
One such technique used for power gating of an IC includes using switching devices in a ring configuration. In the ring configuration, the switching devices are placed in a ring pattern around a switchable portion of the IC. A limitation of the ring configuration approach is the additional area needed to support the separate “switched” portion of the IC and the unswitched or “always-on” portion. Sizing of the switching devices, which includes determining the optimal area of a switch cell necessary to turn on or off the target block of the “switched” portion of the IC, is especially challenging to designers. The challenge is particularly difficult when a majority of a design may need to be part of the “switched” portion.
Accordingly, a need exists for a technique that can implement power gating in an IC and overcomes these limitations. The present invention addresses such a need.